1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing microstructure devices, such as microelectronic components in the form of integrated circuits and the like, and, more particularly, to the formation of stressed material layers in microstructure devices in order to adjust specific device characteristics, such as local charge carrier mobilities in channel regions of a field effect transistor and the like.
2. Description of the Related Art
During the fabrication of microstructure devices, various material layers are typically formed above an appropriate substrate and these layers are locally treated to obtain specific characteristics as required for the function of the device under consideration. The treatment of material layers may include patterning, i.e., the selective removal or deposition of materials, the modification of the conductivity of, for instance, semiconductor materials and the like. Recently, stress and strain engineering techniques have been established in order to adjust device characteristics in a global and local manner. Stress may occur in nearly any type of microstructure device, due to a thermal mismatch of various material layers and the like, and may require a thorough design of the device and the process flow, since respective stress components and the respective strain induced thereby may have a significant influence on the performance and the integrity of devices. On the other hand, stress and strain intentionally used in microstructure devices may significantly improve device characteristics in terms of performance, as will be exemplarily explained with respect to advanced silicon-based transistor elements, which represent a dominant circuit component of sophisticated integrated circuits.
Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an appropriately doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends, among other things, on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially influences the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors, such as the adaptation and possibly the new development of highly complex process techniques required for patterning extremely scaled device features. Furthermore, some of the measures that are necessary for countering detrimental effects, such as short channel effects, i.e., a reduced controllability of the conductive channel, may have a negative impact on the charge carrier mobility in the channel region. Therefore, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region by modifying the lattice structure in the channel region, for instance by creating tensile or compressive stress so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. Thus, the introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and manufacturing techniques.
Consequently, it has been proposed to introduce, for instance, global strain by means of a silicon/germanium layer or a silicon/carbon layer formed on a silicon substrate to obtain the desired strain in the channel region.
In other approaches, locally created stress produced by, for instance, overlaying layers, spacer elements, trench isolation structures and the like is used to create a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress may strongly depend on the device architecture, process techniques, materials used and the like, since the translation of the locally created stress into strain in the channel region is affected by, for instance, how strongly the channel region is bonded to the buried insulating layer in silicon-on-insulator (SOI) devices or the remaining bulk silicon in bulk devices, how much stress may be created during the formation of respective stressed layers and the like.
As a consequence, in advanced microstructure devices, such as integrated circuits, that are fabricated by using one or more of the above-identified techniques, the device characteristics may significantly depend on the stress levels provided in respective material layers, thereby requiring efficient techniques for monitoring the various stress sources of complex devices. However, the determination of internal stress levels of product substrates in a fast and accurate manner is extremely difficult and, hence, the bending of non-patterned test substrates having formed thereon a stressed material of interest is typically measured. In other cases, destructive Raman and micro-Raman techniques may be used to assess the stress conditions of patterned substrates at various process stages. While the measurement of dedicated non-patterned test substrates may not adequately represent the stress conditions on actual product substrates, the latter test procedures may be time-consuming, thereby providing the measurement results in a highly delayed manner.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.